A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by any-one of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
A computer program listing appendix is submitted on compact disc herewith. The material on and in the computer program listing appendix compact disc is hereby incorporated-by-reference. Two compact discs containing identical material, labeled xe2x80x9cCopy 1xe2x80x9d and xe2x80x9cCopy 2,xe2x80x9d are included herewith as per 37 C.F.R. xc2xa7 1.52. Copy 1 contains the following files (in Unix wc format) identified by the name of the file, the date of creation of the file to Copy 1, and the size of the file in kilobytes: ansichdr.sml, 8 KB, Jun. 19, 2001; ansicout.sml, 22 KB, Jun. 19, 2001; array13 scalar13 nonc.sml, 4 KB, Jun. 19, 2001; arrayscalar.sml, 11, KB, Jun. 19, 2001; blocknets.sml, 2 KB, Jun. 19, 2001; blockscan.sml, 13 KB, Jun. 19, 2001; builder.sml, 15 KB, Jun. 19, 2001; buzzels.sml, 2 KB, Jun. 19, 2001; cbgsmllib.sml, 16 KB, Jun. 19, 2001; check_condition.sml, 7 KB, Jun. 19, 2001; csim4.sml, 6 KB, Jun. 19, 2001; cv2.100.sml, 13 KB, Jun. 19, 2001; cv2core.sml, 60 KB, Jun. 19, 2001; cv2gens.sml, 37 KB, Jun. 19, 2001; cverrors.sml, 3 KB, Jun. 19, 2001; cvmetacmd.sml, 1 KB, Jun. 19, 2001; cvmlinit.sml, 2 KB, Jun. 19, 2001; cwords.sml, 2 KB, Jun. 19, 2001; cxverhdr.sml, 19 KB, Jun. 19, 2001; genpadring.sml, 3 KB, Jun. 19, 2001; mapping_report.sml, 1 KB, Jun. 19, 2001; maths.sml, 7 KB, Jun. 19, 2001; notinuse.sml, 25 KB, Jun. 19, 2001; pandex.sml, 27 KB, Jun. 19, 2001; rendervnl.sml, 26 KB, Jun. 19, 2001; sflatten.sml, 30 KB, Jun. 19, 2001; sfmapping.sml, 1 KB, Jun. 19, 2001; smlnj.sml, 7 KB, Jun. 19, 2001; smlnj_first.sml, 1 KB, Jun. 19, 2001; tableprinter.sml, 5 KB, Jun. 19, 2001; topsoaks.sml, 3 KB, Jun. 19, 2001; verinorm.sml, 114 KB, Jun. 19, 2001; veroptions.sml, 2 KB, Jun. 19, 2001; verxcheck.sml, 17 KB, Jun. 19, 2001; vnlaudit.sml, 2 KB, Jun. 19, 2001; vtoc.sml, 18 KB, Jun. 19, 2001; vtochrbody.sml, 77 KB, Jun. 19, 2001; vtoc_rexpr.sml, 16 KB, Jun. 19, 2001; vtoc_sort.sml, 20 KB, Jun. 19, 2001; vtoc_syscexpr.sml, 3 KB, Jun. 19, 2001; vtoc_widees.sml, 102 KB, Jun. 19, 2001; vtocnative.c, 4 KB, Jun. 19, 2001; and vtocnative.sml, 2 KB, Jun. 19, 2001. Copy 2 is an identical copy of Copy 1.
1. Field of the Invention
The present invention generally relates to the conversion of a hardware description computer language to an alternative programming language. More particularly, the present invention relates to a compiler for converting or translating a hardware description computer language to ANSI C or an object-oriented programming language.
2. State of the Art
Hardware description languages are used to define and simulate the operation of integrated circuit chips. One such hardware description language is Verilog. Verilog is used by hardware designers in industry and academia. It allows a hardware designer to describe hardware designs at a high level of abstraction such as at the architectural or behavioral level as well as the lower implementation levels (i.e., gate and switch levels) leading to integrated circuit chip layouts and chip fabrication. The Verilog language also provides access to computer-aided design tools to aid in the design process at the different design levels. Verilog allows hardware designers to express their design with behavioral constructs, deferring the details of implementation to a later stage of design. An abstract representation helps the designer explore architectural alternatives for integrated circuit chips through simulations and to detect design bottlenecks before detailed design begins. A primary use of the simulations allows the designer to test designs before committing to their fabrication. For example, in the general field of integrated circuit chip design, it is useful for a company that has separate hardware and software teams to have available a program to simulate the behavior of the integrated circuits, and to simulate software executing on the integrated circuits. In addition, the use of hardware description languages allows companies that wish to pass executable models of integrated circuits to customers, to do so.
The Verilog language, and other hardware description languages, have a number of disadvantages. Verilog does not support multi-dimensional arrays, pointers or recursions. In addition, it is much slower than a semantically similar language such as ANSI C. One major reason for the slow computation time of a conventional Verilog simulation is the variable size. Many popular processors support variables of size 1, 8, 16, 32 and 64 bits in their instruction sets and this is reflected directly in common software programming languages, such as C. However, Verilog supports a continuum of variable sizes with some exceeding 1000 bits. Since most computational platforms only support 32 bits, the large variable sizes result in the longer run times. Therefore, it would advantageous to translate Verilog to an object-oriented programming language such as C where the variable size could be optimized to a variable or 1, 8, 16, 32, or 64 bits.
Typically, a compiler is required to translate a high-level language to another high-level language. Compilers are special programs that translate a high-level language into the internal language of a particular computer. Hence it is possible to use the same high-level language program on different platforms by using a separate compiler for each platform. It would be advantageous to translate a hardware description language to ANSI C, C++, JAVA or other object-oriented programming languages. The resulting program could then be compiled by an off the shelf compiler such as GNU C or Visual C to the internal language of the computer.
Hardware description language compilers are also expensive and less readily available than C compilers or object-oriented programming language compilers. Therefore, it is desirable to provide a compiler that converts hardware description languages to ANSI C or object-oriented programming languages to optimize run times, while at the same time allowing more individuals access to the ability to simulate hardware designs.
In general, the present invention is a method for converting computer programs written in hardware description languages, such as Verilog or VHDL, to alternative programming languages, such as C, C++, Java, or other object-oriented programming languages. The conversion of a hardware description language to an alternative programming language is accomplished using a compiler that performs the method of the present invention. Unlike conventional simulations using hardware description languages, simulations using the code generated by the present invention achieve optimizations at run time that reduce the required execution time while providing a user additional control over the simulation.
In one embodiment of the present invention a hardware description language computer program is converted to an alternative programming language. The conversion method involves a series of steps that convert a section of hardware description language into an executable program. Initially, a section of hardware description language is preprocessed to prepare the hardware description language section for conversion to an alternative programming language. Following preprocessing, the hardware description language section is flattened into a single, simplified, module using a simplified flattening process. The flattened code is then compiled into an unordered list of assignments using behavioral elaboration. The unordered list of assignments is sorted to order the assignments within clock groups and dependencies. Unused assignments, or assignments which the user chooses to ignore, are trimmed from the sorted assignments. The remaining sorted assignments are assigned to variables compatible with the alternative programming language. Expressions on the right-hand side of each assignment statement are converted to use the set of operators found in the target language. These expressions may not be quite the same as those in the hardware description language. Once processed in this way, the expressions are directly converted to the alternative programming language. The alternative programming language resulting from this method may be executed to simulate the integrated circuit chip described by the hardware description language section or to simulate software operating on the integrated circuit chip.
The simplified flattening process of the present invention may include calls to a stoplist, a leaveout list, or a mapto list. The stoplist identifies hardware description language modules that are not to be flattened. Instead, programming code, written in an alternative programming language, is associated with the files on the stoplist. The programming code may be identified in a linking file. This programming code is then substituted in the flattened module in place of the identified stoplist module. Similarly, the leaveout list defines those hardware description language modules that are not to be flattened, but rather disregarded, by the method of the present invention. The mapto list is similar to the stoplist, except the mapto list allows a user to define preprogrammed code to be substituted for hardware description language functions or tasks. Thus, certain hardware description language functions or tasks identified in the mapto list are replaced during the flattening step with preprogrammed code.
In an alternate embodiment of the present invention, multiple compilations created using the method of the present invention are linked together to model or simulate a large hardware description language program. For example, a large hardware description language program consisting of multiple modules may be divided into subsets of modules. Each module subset may be compiled to produce code of an alternative programming language that models the module subset. The compilations of the module subsets may be linked, providing an efficient method to create a simulation for a large hardware description language program.
The methods of the present invention convert a hardware description language computer program to an alternative programming language such as C, C++, Java, or other object-oriented language to simulate an integrated circuit chip or software operating thereon. In doing so, the run time efficiency of the simulation is improved.